| 摘要 |
PROBLEM TO BE SOLVED: To make simulation in an event driven method at high speed by converting an HDL described in a net list format into an RTL description by reducing the number of events. SOLUTION: A logic circuit reading section 18 reads into a logic circuit storage 20 a logic circuit described by the HDL in the net list format and a lower-level logic circuit (lower-level module) described by the RTL format in a library corresponding to an instance in the logic circuit. A library hierarchy expansion section 22 converts into the RTL format by expanding the library hierarchy to the instance in the logic circuit. A substitution sentence erasure section 24 substitutes and erases the substitution sentence in the logic circuit converted into the RTL format. A logic circuit output section 26 outputs the logic circuit of which conversion is completed in the RTL format. When the logic circuit in a library 16 is described by the HDL in the net list format, the HDL in the net list format is converted into the HDL of the RTL format, similar to the case of the logic circuit. COPYRIGHT: (C)2008,JPO&INPIT
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