发明名称 CORRECTION METHOD AND CORRECTION SYSTEM FOR DESIGN DATA OR MASK DATA, VALIDATION METHOD AND VALIDATION SYSTEM FOR DESIGN DATA OR MASK DATA, YIELD ESTIMATION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD FOR IMPROVING DESIGN RULE, METHOD FOR PRODUCING MASK, AND METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide validation and correction methods and the like for mask data for ensuring the process spec after OPC or process proximity effect correction (PPC) in a short period of time without reproducing a mask by preliminarily extracting a pattern which becomes critical in a process and correcting the pattern. <P>SOLUTION: The method includes steps of: (S0, S1) applying a resist, exposing and developing the resist with an evaluation mask including a pattern which becomes critical in a process, etching a circuit material using the resist having been developed, and measuring pattern sizes of the developed resist and the etched circuit material; (S2) extracting parameter numerical condition for preventing the design data from being critical after OPC or PPC, as a rule or a model on the basis of the measured pattern sizes; (S3) extracting a critical pattern not satisfying the foregoing rule or model from the design data or mask data using the extracted rule or model; and (S5) correcting the critical pattern. <P>COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008033277(A) 申请公布日期 2008.02.14
申请号 JP20070161906 申请日期 2007.06.19
申请人 SHARP CORP 发明人 HARASAKI KATSUHIKO
分类号 G03F1/36;G03F1/68;G03F1/70;G06F17/50 主分类号 G03F1/36
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