| 摘要 |
A pulse generator 1500 is triggered by a rising clock edge to provide narrow complementary clock pulses for clocking a pulsed latch (figures 9-12). When the narrow pulses have terminated neither the pull-up nor pull-down branches of the circuit 1506 are conducting, but the half latch 1507,1508 is operable to maintain a good logic low level at the output node of 1506. The output transistor 1508 of the half-latch may be disabled when the input clock signal goes low (figure 16), thereby preventing contention between the half-latch and the pull-up branch of the circuit 1506. A similar pulse generator using a NOR gate and a keeper with PMOS output is disclosed (figure 17). The pulse generators may be disabled (figures 15,16, 20,21) so that they do not respond to the clock input. |
