发明名称 |
Coverage decoder circuit for performance counter |
摘要 |
Circuitry for use with a general purpose performance counter ("GPPC") connected to a bus carrying a plurality of encoded state coverage signals indicative of test coverage in a logic design, wherein the circuitry is operable to decode and capture the encoded coverage information. A selection circuit associated with the GPPC is operable to select the encoded state coverage signals from a multi-bit event signal on the bus. A line decoder coupled to the selection circuit decodes the encoded state coverage signals into N one-hot signals, which are asserted based on coverage of corresponding states during test. A capture circuit is operable to capture the N one-hot signals for further processing.
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申请公布号 |
US7275191(B2) |
申请公布日期 |
2007.09.25 |
申请号 |
US20030635372 |
申请日期 |
2003.08.06 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
ADKISSON RICHARD W. |
分类号 |
G01R31/28;G06F11/00;G06F11/34;H02H3/05 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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