发明名称 EPITAXIAL WAFER FOR TRANSISTOR, AND TRANSISTOR
摘要 PROBLEM TO BE SOLVED: To reduce resistance of an n-type InGaAs non-alloy layer. SOLUTION: On a semi-insulating GaAs substrate 1, an n-type sub-collector layer 2, an n-type collector layer 3, a p-type base layer 4, an n-type emitter layer 5, and an n-type InGaAs non-alloy layer 10 are formed in order. The n-type InGaAs non-alloy layer 10 is composed of an n-type InGaAs graded layer 10a in which an In composition is inhomogenous (inhomogenous composition layer) and an n-type InGaAs homogenous layer 9 in which the In composition is homogenous, on the graded layer 10a. The graded layer 10a is composed of a first graded layer 7 (first layer) in which In composition is low, and a second graded layer 8 (second layer) in which the In composition is higher than that in the first graded layer 7. In the first graded layer 7, the background concentration of C (carbon) in the In composition is suppressed, and Si is doped for obtaining carrier concentration higher than that in the case of doping Se as an n-type dopant. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007189200(A) 申请公布日期 2007.07.26
申请号 JP20060313513 申请日期 2006.11.20
申请人 HITACHI CABLE LTD 发明人 MORIYA YOSHIHIKO
分类号 H01L21/331;H01L29/205;H01L29/207;H01L29/737 主分类号 H01L21/331
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