| 摘要 |
<p>A negative output regulator circuit (24) is provided with clamp circuits CLP (X1, X2, Q1, Q2), which detect a current generated when the output of a negative voltage (VM) is stopped and fixing the voltage of an output end (T2) at a prescribed value. Generation of a positive voltage at an output terminal is suppressed without increasing chip size nor making the sequence complicated.</p> |
