| 摘要 |
<p>The disclosure concerns a semiconductor memory device includes a memory cell array including memory cells; word lines; bit lines; a counter cell array including counter cells provided corresponding to the word lines and storing the number of times of activating the word lines; an adder incrementing the number of times of activating the word lines which is read out from the counter cell array, when data is read or written in the memory cell; a counter buffer circuit temporarily storing the number of times of activating the word lines, and writing back the incremented number of times of activating the word lines into the counter cell array; and a sense amplifier executing a refresh operation during a data read cycle or a data write cycle, when the number of times of activating one of the word lines has reached a predetermined value.</p> |
