发明名称 Duty cycle measurement circuit
摘要 A duty cycle measurement circuit and method of operation is described that is particularly well adapted for use in microelectronics devices. In one embodiment, the circuit the includes a clock signal selector to alternately select the high or the low phase of an input clock signal, a sweep circuit to sweep a timing parameter through a range, and a latch to compare the clock signal to the timing parameter and generate a result.
申请公布号 US2007075753(A1) 申请公布日期 2007.04.05
申请号 US20050240761 申请日期 2005.09.30
申请人 PARKER RACHAEL;NEIDENGARD MARK;ABEDIN SHAMSUL 发明人 PARKER RACHAEL;NEIDENGARD MARK;ABEDIN SHAMSUL
分类号 H03B19/00 主分类号 H03B19/00
代理机构 代理人
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