METHOD FOR ANALYZING LAYOUT OF SEMICONDUCTOR INTEGRATE CIRCUIT DEVICE, SYSTEM FOR ANALYZING LAYOUT OF SEMICONDUCTOR INTEGRATE CIRCUIT DEVICE, STANDARD CELL LIBRARY, MASK AND SEMICONDUCTOR INTEGRATE CIRCUIT DEVICE,申请号KR20060006959-传众专利搜索

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发明名称	METHOD FOR ANALYZING LAYOUT OF SEMICONDUCTOR INTEGRATE CIRCUIT DEVICE, SYSTEM FOR ANALYZING LAYOUT OF SEMICONDUCTOR INTEGRATE CIRCUIT DEVICE, STANDARD CELL LIBRARY, MASK AND SEMICONDUCTOR INTEGRATE CIRCUIT DEVICE
摘要
申请公布号	KR100703982(B1)	申请公布日期	2007.03.29
申请号	KR20060006959	申请日期	2006.01.23
申请人	SAMSUNG ELECTRONICS CO., LTD.	发明人	BAE, CHOEL HWYI;BAEK, GWANG HYEON;CHO, MIN GEON
分类号	H01L21/66	主分类号	H01L21/66
代理机构		代理人
主权项
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