| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an integrated circuit apparatus and electronic equipment in which control of P type and N type MOS transistors constituting a transfer gate connected to a memory cell at the time of reading and erasing modes and programming can be changed to secure breakdown voltage and a sub-word line decoder which can be reduced in area is mounted. <P>SOLUTION: A first transfer gate 240 provided between a memory cell MC and a bit line BL has P type and N type MOS transistors Xfer (P, N) connected to a sub-word line decoder SWDec. The sub-word line decoder is constituted of six transistors in total including second and third transfer gates 610, 630 and two transistors 600, 620, an output line of a column driver CLDrv is connected to a source of one side 610 out of the second and the third transfer gates, and an inversion program line XPGM is connected to a source of the other side 630 out of the second and the third transfer gates. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
