发明名称 CIRCUIT AUTOMATIC GENERATION DEVICE AND METHOD
摘要 PROBLEM TO BE SOLVED: To automatically generate the uppermost hierarchy circuit for a semiconductor integrated circuit only by inputting circuit specifications. SOLUTION: This circuit automatic generation device is provided with a storage means 4 storing input/output information and connection destination information about each functional circuit, test mode generation specification generating a test mode signal, test specifications added to the functional circuit, terminal test specifications designating the input/output direction and the connection destination information for the terminal, and input/output information and connection destination information for the uppermost hierarchy circuit, a connection information confirmation means 5 determining presence/absence of a connection failure of the functional circuit, a test mode generation circuit generation means 10 generating a test mode generation circuit, a test specification addition functional circuit generation means 9 generating a functional circuit to which the test specifications are added, a terminal test circuit generation means 11 generating a terminal test circuit, and an uppermost hierarchy circuit generation means 8 generating the uppermost hierarchy circuit from the test mode generation specifications, the test terminal specifications, the input/output information and the connection destination circuit information for the functional circuit, the test specifications added to the functional circuit, and the input/output information and the connection destination circuit information about the uppermost hierarchy circuit. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006285947(A) 申请公布日期 2006.10.19
申请号 JP20050255054 申请日期 2005.09.02
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 OHARA YASUSHI
分类号 G06F17/50 主分类号 G06F17/50
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