发明名称 CONNECTION ERROR AVOIDANCE IN APPARATUS CONNECTED TO A POWER SUPPLY
摘要 A logic arrangement for reducing incidence of errors in connections between a power consumer apparatus and a power supply apparatus, comprises: a pattern-generating component for generating an identifiable pattern for a patterned load to be drawn from a power supply connection; a load-drawing component, responsive to the pattern-generating component, 10 for drawing the patterned load from the power supply connection; and a testing component at the power consumer apparatus for testing across a signal connection for a responsive supply to satisfy demand for the patterned load by the power supply apparatus. The logic arrangement may further be embodied as a system or as a computer program.
申请公布号 WO2006084783(A2) 申请公布日期 2006.08.17
申请号 WO2006EP50286 申请日期 2006.01.18
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION;HYATT, STEVE, JOHN;JUDD, IAN, DAVID;NICHOLSON, ROBERT, BRUCE;QUELCH, PAUL, JONATHAN;RANDLE, STEPHEN, ARTHUR;SCALES, WILLIAM, JAMES 发明人 HYATT, STEVE, JOHN;JUDD, IAN, DAVID;NICHOLSON, ROBERT, BRUCE;QUELCH, PAUL, JONATHAN;RANDLE, STEPHEN, ARTHUR;SCALES, WILLIAM, JAMES
分类号 G06F1/26;G06F11/22 主分类号 G06F1/26
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