发明名称 Semiconductor memory device having mis-type transistors
摘要 According to one aspect of the present invention, a semiconductor memory device has: a semiconductor layer formed on an insulating film; and a memory cell array including a matrix arrangement of a plurality of memory cells each made up of first and second transistors connected in series, one side of each memory cell being connected to a bit line and the other side of each memory cell being supplied with a reference potential, and according to another aspect of the present invention, a semiconductor memory device manufacturing method includes: forming an oxide layer and a silicon active layer on a semiconductor substrate; forming an element isolation region for separating said silicon active layer into discrete element-forming regions to be substantially flush with said silicon active layer; forming gate electrode of paired two transistors by depositing a gate electrode material on said silicon active layer and patterning it; injecting predetermined ions into a region for forming a diffusion layer in, using said gate electrodes as an ion injection mask; forming said paired transistors by activating the injected ions through a heat process; and forming a first gate line connected to the gate electrode of one of said paired transistors and a second gate line connected to the gate electrode of the other of said paired transistors.
申请公布号 US7081653(B2) 申请公布日期 2006.07.25
申请号 US20020075464 申请日期 2002.02.15
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KAWANAKA SHIGERU
分类号 H01L27/01;H01L29/78;G11C11/405;H01L21/8238;H01L21/8242;H01L21/84;H01L27/08;H01L27/092;H01L27/108;H01L27/11;H01L27/12;H01L29/786 主分类号 H01L27/01
代理机构 代理人
主权项
地址