| 摘要 |
A phase locked loop (PLL) circuit having a multi-level voltage-current converter and a clock phase locking method using multi-level voltage-current conversion are described. The phase locked loop (PLL) circuit generates an output clock signal that is phase-locked to a reference clock signal. Further, the PLL circuit includes a phase detecting unit, a charge pump unit, a current-voltage converting unit, and a voltage control oscillator. The phase detecting unit detects a phase difference between the reference clock signal and the output clock signal. The charge pump unit generates a pumping voltage in response to an up signal or down signal output from the phase detector. The current-voltage converting unit receives the pumping voltage, converts the pumping voltage into a predetermined first current, and outputs a tuning voltage in response to predetermined selection signals. The voltage control oscillator generates the output clock signal with a frequency that is proportional to the tuning voltage.
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