| 摘要 |
A CMOS static random access memory (SRAM) array with dynamically asymmetric cells, an integrated circuit (IC) chip including the SRAM and a method of accessing data in the SRAM. Each column of cells is connected to a pair of column supply lines supplying power to the column. During each SRAM access, a higher voltage is applied to one column supply line in each pair of the columns being accessed to unbalance cells in the columns being accessed. Unbalanced cells become asymmetric during accesses and the supply imbalance favors the data state being written/read.
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