发明名称 |
Power grid layout techniques on integrated circuits |
摘要 |
Techniques are provided for reducing the power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within an integrated circuit across conductive traces. The conductive traces are coupled to solder bumps that receive power supply voltages from an external source. Alternate ones of the traces receive a high power supply voltage V<SUB>DD </SUB>and a low power supply voltage V<SUB>SS</SUB>. The conductive traces reduce the voltage drop in the power supply voltages by providing shorter paths to route the power supply voltages to circuit elements on the integrated circuit. |
申请公布号 |
US2006081984(A1) |
申请公布日期 |
2006.04.20 |
申请号 |
US20050237304 |
申请日期 |
2005.09.27 |
申请人 |
TELAIRITY SEMICONDUCTOR, INC. |
发明人 |
CAMPBELL JOHN;STEVENS KIM R.;DIGREGORIO LUIGI |
分类号 |
H01L21/3205;H01L23/48;H01L21/82;H01L21/822;H01L23/52;H01L23/528;H01L27/04 |
主分类号 |
H01L21/3205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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