发明名称 Integrated circuit device provided with series-connected TC parallel unit ferroelectric memory and method for testing the same
摘要 An integrated circuit device comprises a memory cell block, a word line selecting circuit and a driving circuit. The memory cell block comprises memory cells connected in series. The memory cell comprises a cell transistor including a gate which is connected to a word line, and a ferroelectric capacitor connected to terminals of the cell transistor. The word line selecting circuit successively selects the word lines connected to the cell transistors in the memory cells in the memory cell block in response to address signals successively input from an outside of the device, during an active cycle. The driving circuit applies a given voltage between ends of a current path provided of the cell transistors in the memory cells in the memory cell block, during a time period for which the word lines connected to the cell transistors are successively selected by the word line selecting circuit.
申请公布号 US2006077703(A1) 申请公布日期 2006.04.13
申请号 US20050109769 申请日期 2005.04.20
申请人 MIYAKAWA TADASHI;TAKASHIMA DAISABURO;SHIRATAKE SHINICHIRO 发明人 MIYAKAWA TADASHI;TAKASHIMA DAISABURO;SHIRATAKE SHINICHIRO
分类号 G11C11/22 主分类号 G11C11/22
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