发明名称 |
INTEGRATED APPROACH FOR DESIGN, SIMULATION AND VERIFICATION OF MONOLITHIC, SILICON-BASED OPTO-ELECTRONIC CIRCUITS |
摘要 |
<p>Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design. The results of the co-simulation are compared to the results of the co-verification, with alterations made in the logic design and/or the physical layout until the desired operating parameters are obtained. Once the desired results are generated, conventional wafer-level fabrication operations are then considered to provide a final product ("tape out").</p> |
申请公布号 |
WO2006007474(A2) |
申请公布日期 |
2006.01.19 |
申请号 |
WO2005US22254 |
申请日期 |
2005.06.22 |
申请人 |
SIOPTICAL, INC.;SHASTRI, KALPENDU;PATHAK, SOHAM;GOTHOSKAR, PRAKASH;MOSINSKIS, PAULIUS;DAMA, BIPIN |
发明人 |
SHASTRI, KALPENDU;PATHAK, SOHAM;GOTHOSKAR, PRAKASH;MOSINSKIS, PAULIUS;DAMA, BIPIN |
分类号 |
G06F17/50;G06G7/62 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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地址 |
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