| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a digital/analog consolidation semiconductor integrated circuit which is highly reliable and capable of suppressing inconveniences by noise occurred in a digital circuit sufficiently. <P>SOLUTION: A digital/analog consolidation semiconductor integrated circuit 10 for consolidating an analog circuit 5 and a digital circuit 6 is provided with: a noise generating means 9 for generating noises of the digital circuit 6; a clock phase regulating means 7 for regulating phases of a clock to be inputted to the digital circuit 6; and an analysis means 8 for analyzing characteristics of the analog circuit 5. On the basis of the analysis results of an analysis tool 8 at the time generating the noises by the noise generating means 9, phase adjustment is performed by a clock phase adjustment means 7. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
