发明名称 |
Structure and method of vertical transistor DRAM cell having a low leakage buried strap |
摘要 |
A structure and method is disclosed herein for a vertical transistor DRAM cell having a low leakage buried strap outdiffusion conductively connecting a storage capacitor in a lower portion of a trench to a vertical transistor thereabove. In the disclosed structure and method, the buried strap outdiffusion (BSOD) extends along a portion of the isolation collar having reduced thickness, the reduced thickness being substantially less than the thickness of the isolation collar otherwise. In a particular embodiment, a self-aligned lightly doped drain (LDD) extension is formed, extending between the BSOD and the vertical transistor above the LDD.
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申请公布号 |
US6979851(B2) |
申请公布日期 |
2005.12.27 |
申请号 |
US20020265558 |
申请日期 |
2002.10.04 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CHIDAMBARRAO DURESETI;MANDELMAN JACK ALLAN;RADENS CARL JOHN |
分类号 |
G11C11/24;H01L21/8242;H01L29/76;(IPC1-7):H01L29/76 |
主分类号 |
G11C11/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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