发明名称 |
CAPACITANCE MULTIPLIER FOR A PLL LOOP FILTER |
摘要 |
<p>A capacitance multiplier includes a cascade of a plurality of current amplifiers with each current amplifier having a respective current gain Ki. In addition, the capacitance multiplier includes a capacitor coupled in parallel across the cascade of current amplifiers. Such a capacitance multiplier occupies a smaller area with higher capacitance gain but with low power consumption.</p> |
申请公布号 |
KR20050118533(A) |
申请公布日期 |
2005.12.19 |
申请号 |
KR20040043670 |
申请日期 |
2004.06.14 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM, JAE WAN |
分类号 |
H03L7/08;H03H11/48;H03L7/06;H03L7/089;H03L7/093;(IPC1-7):H03L7/08 |
主分类号 |
H03L7/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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