| 摘要 |
Pattern-dependent jitters are reduced, and timing errors of timing pulse signals are decreased in a timing generator. In a timing generator 20 , a delaying circuit (variable delaying means, clock signal delaying circuit) 32 is disposed on an input terminal side of a clock signal, not an output terminal side of a flip-flop 31 in a signal input/output circuit 30 having the flip-flop (reference signal delaying means) 31 which outputs an output signal in accordance with an input timing of the clock signal, and the clock signal is delayed. The clock signal delaying circuit 32 may be replaced with a phase locked loop circuit 34.
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