| 摘要 |
A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M 8 and M 9 are respectively connected, and a pair of differential MOS transistors M 1 and M 2 having gates between which a switch SW 1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M 9 . A switch SW 2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M 1 , and a switch SW 3 is connected between the output VO and the gate of the MOS transistor M 8 . During the offset-cancel preparation period, the switches SW 1 and SW 3 are on and the switch SW 2 is off. Next, the switches SW 1 to SW 3 are turned over, consequently outputting offset-canceled potential VO.
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