| 摘要 |
A hardware-configurable digital filter is adaptable for providing multiple filtering modes. In one embodiment, the digital filter includes a register-based array of logic circuitry, computational circuitry and mode selection circuitry. By reconfiguring data flow within the logic circuitry and the computational circuitry, the mode selection circuitry switches the digital filter between different ones of the multiple filtering modes. Each of the multiplication and addition logic circuits has outputs and inputs selectably coupled to the other of the multiplication and addition logic circuits along a Y direction, with the selectivity being responsive to the mode selection circuitry for arranging the registers as being functionally linear or functionally nonlinear. In a more specific embodiment the filtering modes include polyphase filtering and general purpose filtering applications (such as FIR filtering), and in another more specific embodiment the filtering modes include polyphase direct filtering, polyphase transposed filtering, and at least one general purpose filtering. A specific example application of the above type of digital filter is directed to filtering video pixel components, for example, in resizing a horizontal line of pixels.
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