发明名称 |
CACHE BANK INTERFACE UNIT |
摘要 |
A server including an application processor chip. The application processor chip includes a plurality of processing cores, where each of the processing cores are multi-threaded. A plurality of cache bank memories is included. Each of the cache bank memories include a tag array region configured to store data associated with each line of the cache bank memories, a data array region configured to store the data of the cache bank memories, an access pipeline configured to handle accesses from the plurality of processing cores, and a miss handling control unit configured to control the sequencing of cache-line transfers between a corresponding cache bank memory and a main memory. A crossbar enabling communication between the plurality of processing cores and the plurality of cache bank memories is provided. |
申请公布号 |
WO2005020080(A3) |
申请公布日期 |
2005.10.27 |
申请号 |
WO2004US24911 |
申请日期 |
2004.07.30 |
申请人 |
SUN MICROSYSTEMS, INC.;OLUKOTUN, KUNLE, A. |
发明人 |
OLUKOTUN, KUNLE, A. |
分类号 |
G06F9/38;G06F12/08;G06F15/78 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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