| 摘要 |
A gate array design method is disclosed for an integrated circuit whose core region is divided into a plurality of areas, each of which includes sequential circuit sites. The method is composed of providing a netlist and a site array data, allocating each of multi-phase clock signals used in the integrated circuit to each of the plurality of areas to produce an allocation data representative of an association of the multi-phase clock signals to the plurality of areas, modifying the site array data based on said allocation data, modifying the netlist to allow the netlist to correspond to the modified site array data, and placing and routing the integrated circuit based on the modified netlist and site array data. The site array data is modified to allow each of the plurality of areas to include sequential circuit cells which are provided with a same one of the multi-phase clock signals.
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