| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of shortening address access time even when a conventional structure is used as it is. SOLUTION: A synchronous memory device wherein additive latency is provided, a read command or write command is entered, and each command is executed by the operations of a plurality of internal commands is provided with a clock buffer for receiving a clock from the outside and outputting it, and a control means for controlling, when the additive latency is not "0", one of the plurality of internal command operations corresponding to the read command or write command to be executed by predetermined timing before tRCD timing. COPYRIGHT: (C)2005,JPO&NCIPI
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