| 摘要 |
A phase detector in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain that is clocked with a first clock signal and second circuitry disposed in a second clock domain that is clocked with a second clock signal. The phase detector includes means for sampling the second clock signal with the first clock signal to generate a sampled clock signal. By tracking movement in a predetermined transition in the sampled clock signal, the phase detector is operable to determine the phase difference between the first and second clock signals.
|
