发明名称 Identifying execution ready instructions and allocating ports associated with execution resources in an out-of-order processor
摘要 A find-instructions-and-allocate-ports (FIAP) circuit and method are provided for quickly and efficiently locating one or more instructions that are ready for execution during a launch cycle in an out of order processor and allocating one or more ports associated with one or more execution resources to such ready instructions during the launch cycle. In architecture, the processor includes an instruction reordering mechanism, for example, a queue, having a plurality of slots for temporarily storing a plurality of respective instructions. Instructions can be executed in an out of order sequence from the queue. Each slot is provided with the FIAP circuit for causing and preventing launching, when appropriate, of their respective instruction. A plurality of signals is propagated successively through the FIAP circuits of the queue that causes the queue to launch a predefined plurality of the instructions, which corresponds to a predefined plurality of ports associated with the one or more execution resources. As propagation of the set of signals occurs through each slot, the set of signals indicates to the slot when and which of the one or more ports are available for each said instruction and when none of the ports are available.
申请公布号 US6892294(B1) 申请公布日期 2005.05.10
申请号 US20000497533 申请日期 2000.02.03
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 NAFFZIGER SAMUEL D
分类号 G06F9/38;G06F9/30;(IPC1-7):G06F9/30 主分类号 G06F9/38
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