| 摘要 |
An architecture for a biquad (70), second-order infinite impulse response (IIR) digital filter, that is capable of operating at maximum efficiency, is disclosed. The biquad (70) includes coefficient memory (50) and data memory (52), along with control circuitry (53) that loads values from these memories (50, 52) into a coefficient register (52) and a data register (54), respectively. A multiplier (55) multiplies the values in the coefficient register (52) and data register (54), with the resulting product being stored in a product register (58). An accumulator (59) adds successive product results to derive a new output value in each instance of the IIR filter. A shadow register (60) temporarily stores the output of the accumulator (59) from a previous instance, permitting this output to be stored in the data memory (52) at a later time in the sequence. This permits the order of operations in the second and successive biquads to be altered so that each successive biquad instance can start well before the previous result is derived; as a result, the multiplier (55) is fed with values each cycle, enabling maximum efficiency operation.
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