发明名称 |
Semiconductor memory having a flexible dual-bank architecture with improved row decoding |
摘要 |
A semiconductor memory includes a plurality of memory array partitioned into first and second memory banks in correspondence with one of a plurality of mask options such that the first memory bank includes at least one but less than all of the plurality of memory arrays and the second memory bank includes a corresponding remainder of the plurality of memory arrays. A first horizontal global row decoder is configured to receive a first subset of addresses for the first memory bank and in response provide a first plurality of predecoded row address signals on a first plurality of lines extending only across the at least one but less than all of the plurality of memory arrays. A second horizontal global row decoder is configured to receive a first subset of addresses for the second memory bank and in response provide a second plurality of predecoded row address signals on a second plurality of lines extending only across the corresponding remainder of the plurality of memory arrays.
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申请公布号 |
US2004246806(A1) |
申请公布日期 |
2004.12.09 |
申请号 |
US20040768398 |
申请日期 |
2004.01.29 |
申请人 |
WINBOND ELECTRONICS CORPORATION |
发明人 |
HA CHANG WAN |
分类号 |
G11C8/10;G11C8/14;G11C16/08;G11C16/20;(IPC1-7):G11C8/00 |
主分类号 |
G11C8/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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