| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can be reduced in cell area and to provide its designing method. SOLUTION: By standardizing the semiconductor integrated circuit so that the gate electrodes GE121 to GE128 are arranged on gate grids, the gate electrodes of MOS (metal oxide semiconductor) transistors arranged at an upper and a lower part in Fig. hardly vary in a space between them, and a matter of discrepancies in phase as to patterning can be solved, and the semiconductor integrated circuit can be much reduced in size. Input/output terminals I/O121 to I/O128 are arranged while taking the misalignment of gate grids with metal pin grids into consideration. Diffusion layers NS121 and NS122 and PS121 and PS122 for applying a board bias potential to N wells and P wells are arranged as board potential setting cells in a region where the MOS transistors are arranged, thereby, an impurity diffusion layer for applying a board potential is not required to be provided in a power voltage line and a grounding voltage line, and the power voltage line and grounding voltage line can be reduced in width d1. COPYRIGHT: (C)2005,JPO&NCIPI
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