发明名称 METHOD FOR DESIGNING SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor device for quickly controlling crosstalk by extracting a parasitic element generated between wires in accordance with request accuracy and bypassing the parasitic element while considering an arrangement area or a wiring route at automatic arrangement/wiring and to provide a method for designing the semiconductor device. SOLUTION: After temporarily wiring all networks by a temporary wiring process 100, a parasitic element generated between wires is extracted in accordance with wiring density by a wiring density extraction process 101, and in determining a wiring route in a wiring route determination process 104 by dividing the whole target wires like a grating and setting a coefficient calculated on the basis of a previously prepared parasitic element table 103 in a parasitic element coefficient setting process 102, a layout reducing the influence of crosstalk can be quickly obtained at necessary and sufficient accuracy by wiring networks while considering complicated crosstalk causality (e.g. strength of crosstalk received from another network or applied to another network). COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004240838(A) 申请公布日期 2004.08.26
申请号 JP20030030980 申请日期 2003.02.07
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KAWAI TADAYUKI;TAMURA JINICHI
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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