发明名称 Split gate flash memory cell and manufacturing method thereof
摘要 A split gate flash memory cell includes a substrate having a trench, a stack structure disposed on the substrate, wherein the stack structure includes a tunneling dielectric layer, a floating gate and a cap layer; a first inter-gate dielectric layer and a second inter-gate dielectric layer disposed on the sidewalls of the stack structure, wherein the first inter-gate dielectric layer is contiguous to the top of the trench; a selective gate disposed on the sidwalls of the first inter-gate dielectric layer and the trench; a selective gate dielectric layer disposed between the selective gate and the substrate; a source region configured in the substrate beside the side of the stack structure with the second inter-gate dielectric layer; and a drain region configured at the bottom of the trench beside one side of the selective gate.
申请公布号 US6768162(B1) 申请公布日期 2004.07.27
申请号 US20030604612 申请日期 2003.08.05
申请人 POWERCHIP SEMICONDUCTOR CORP. 发明人 CHANG KO-HSING;HSU HANN-JYE
分类号 H01L21/8247;H01L29/423;H01L29/788;(IPC1-7):H01L29/788 主分类号 H01L21/8247
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