DCT ARITHMETIC DEVICE

摘要

There is provided a DCT processor for performing at least one of DCT operation and inverse DCT operation for image data in unit blocks having different sizes. This DCT processor is provided with a bit slice circuit (102) for outputting, bit by bit, the pixel data inputted for each column or row; a first butterfly operation circuit (103) for subjecting the output data of the bit slice circuit (102) to butterfly operation; a ROM address generation circuit (104) for generating continuous ROM addresses; an RAC (105) for reading the data corresponding to the ROM addresses from ROMs (ROM0 SIMILAR ROM7) and accumulating the data by accumulation circuits (51a SIMILAR 51h); and a second butterfly operation circuit 106 for subjecting the output data of the RAC 105 to butterfly operation. <IMAGE>