发明名称 |
Multi-port integrated cache |
摘要 |
A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.
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申请公布号 |
US2004088489(A1) |
申请公布日期 |
2004.05.06 |
申请号 |
US20030687460 |
申请日期 |
2003.10.15 |
申请人 |
SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER |
发明人 |
HIRONAKA TETSUO;MATTAUSCH HANS JURGEN;KOIDE TETSUSHI;HIRAKAWA TAI;JOHGUCHI KOH |
分类号 |
G06F9/38;G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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