发明名称 Interlocking conductor method for bonding wafers to produce stacked integrated circuits
摘要 An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. Plugs that extend from one surface of the wafer into the wafer are used to provide vertical connections and to bond the wafers together. A stacked integrated circuit is constructed by bonding the front side of a new wafer to a wafer in the stack and then thinning the backside of the new wafer to a thickness that leaves a portion of the plugs extending above the surface of the backside of the thinned wafer. The elevated plug ends can then be used to bond another wafer by bonding to pads on the front side of that wafer. The mating bonding pads can include depressed regions that mate to the elevated plug ends.
申请公布号 US2004048459(A1) 申请公布日期 2004.03.11
申请号 US20030658132 申请日期 2003.09.08
申请人 PATTI ROBERT 发明人 PATTI ROBERT
分类号 H01L21/768;H01L23/48;H01L25/065;(IPC1-7):H01L21/30;H01L21/44;H01L21/46 主分类号 H01L21/768
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