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发明名称
Process for epitaxy on a silicon substrate containing zones highly doped with arsenic
摘要
申请公布号
EP0897024(B1)
申请公布日期
2004.02.11
申请号
EP19980410085
申请日期
1998.07.28
申请人
STMICROELECTRONICS S.A.;FRANCE TELECOM
发明人
DUTARTRE, DIDIER;JERIER, PATRICK
分类号
C30B29/06;C23C16/24;C30B25/02;C30B25/20;H01L21/205;(IPC1-7):C30B25/02
主分类号
C30B29/06
代理机构
代理人
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