发明名称 |
Method and device for frequency synthesis using a phase locked loop |
摘要 |
A frequency synthesis method using a phase locked loop including a phase comparator. The method includes switching from a fractional frequency division operating mode to an integer frequency division operating mode after a time or time-delay for stabilizing operation of the loop has elapsed. The method is characterized in that it consists of effecting the operating mode switching by masking or eliminating a portion of the pulses of a reference signal (Sref) and a comparison signal (Scomp) before they are applied to inputs of the phase comparator (3).
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申请公布号 |
US6680628(B2) |
申请公布日期 |
2004.01.20 |
申请号 |
US20020069444 |
申请日期 |
2002.05.22 |
申请人 |
ALCATEL |
发明人 |
BRUNET ARNAUD;RIEUBON SEBASTIEN |
分类号 |
H03L7/089;H03L7/197;(IPC1-7):H03B21/00 |
主分类号 |
H03L7/089 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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