| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem of requiring a long design period for requiring to repeatedly performing the designation of the arrangement wiring area of a hierarchical block by a designer and optimization processing by an arrangement wiring circuit optimizing part 7 until obtaining an arrangeable wirable floor plan, and requiring an experienced excellent engineer for obtaining the good-quality floor plan. SOLUTION: The arrangement position of a logic seed 33 on each hierarchical block is determined, and a cell belonging to the hierarchical block is arranged in the peripheral area of the arrangement position of the logic seed 33, and the arrangement wiring area 36 of the hierarchical blocks is determined by taking into consideration the arrangement result of the cell. COPYRIGHT: (C)2004,JPO
|
