| 摘要 |
PROBLEM TO BE SOLVED: To surely transfer a start signal STH between data side drivers in cascade connection. SOLUTION: In the cascade-connection of the data side drivers 40, the first stage data side driver uses its changeover switch 41 to select a basic clock signal CLKA as a clock signal supplied to a start signal read circuit 10 and the data side drivers of the second and succeeding stages select a delayed clock signal CLKB resulting from delaying the basic clock signal CLKA by each delay circuit 9. Thus, the first stage data side driver at a leading edge of a substantial read pulse of the basic clock signal CLKA and the second and succeeding stage data side drivers at a leading edge of a substantial read pulse of the delayed clock signal CLKB can normally read the start signal STH, respectively. COPYRIGHT: (C)2004,JPO
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