| 摘要 |
PURPOSE: A method for manufacturing an MPDL(Merged Planar DRAM and Logic) semiconductor device is provided to be capable of reducing chip size by reducing the area of a capacitor. CONSTITUTION: A semiconductor substrate(31) defined by a capacitor and transistor forming region is prepared. After forming the first oxide layer on the substrate, dopants are implanted into the substrate(31) of the capacitor forming region. An MPS(Metastable Polysilicon) layer(39a) is formed on the surface of the implanted substrate. An upper electrode(43a) and a gate electrode(43b) are formed on the capacitor and transistor forming region, respectively. Then, a source/drain region(51) is formed in the substrate of the transistor forming region.
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