| 摘要 |
A circuit that synchronizes an output clock signal to a second clock signal includes a frequency locked loop circuit that receives the output clock signal and the second clock signal, modifies a frequency of the output clock signal in response to a difference in frequency between the output signal clock signal and the second clock signal to provide an output clock signal having a frequency within a predetermined error band of the frequency of the second clock signal and wherein the frequency locked loop continues to provide the output clock signal in the absence of the second clock signal.
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