Process for reducing the pitch of contact holes, vias, and trench structures in integrated circuits

摘要

An integrated circuit fabrication process to pattern features having reduced pitch is disclosed herein. The process includes reducing the width of a developed exposed area of a patterned photoresist layer provided over a substrate before patterning the substrate. The process further includes additionally patterning the patterned photoresist layer using the previously used mask or reticle to form a first feature and a second feature. The distance between adjacent first and second features is smaller than the distance between either of adjacent first features or adjacent second features.