| 摘要 |
<p>Probabilities of the changeovers of access pages in the same bank and the changes of types of accesses, for instance the change from read to write or from write to read, are reduced and thereby data transmission performance is improved. If respective memory masters (12) want to acquire the memory use right, they assert request signals and, at the same time, fix address signals and read/ write signals. A memory arbitration circuit (13) determines the priority order over the memory use right for the respective memory masters (12), and asserts an acknowledgement signal for a memory master (12) having the highest priority. <IMAGE></p> |
