发明名称 Method of designing semiconductor integrated circuit device, method of analyzing power consumption of circuit and apparatus for analyzing power consumption
摘要 The processing quantity of each description part is estimated through a source code analysis of a system operation description language or through simulation, or power consumption of each function is estimated through an operation description analysis of functions. Predetermined threshold values are set with respect to the processing quantity and the power consumption of each description part or function, so as to determine S/W and H/W implementation, and then, S/W and H/W partitioning is carried out. Thereafter, it is determined whether or not the total processing quantity or the total power consumption satisfies a desired design condition. Also, the S/W and H/W partitioning can be adjusted again in comprehensive consideration of the power consumption and the processing quantity, and the accuracy in the S/W and H/W partitioning can be improved by providing an instruction set simulator with a function to analyze power consumption. Moreover, an interface between S/W and H/W can be generated in the S/W and H/W partitioning so as to be automatically inserted into a S/W implemented part or a H/W implemented part.
申请公布号 US2003088840(A1) 申请公布日期 2003.05.08
申请号 US20020326152 申请日期 2002.12.23
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 YONEZAWA TOMONORI;SASAKI TAKAYUKI;KONDO TAKAHIRO;OTSUKI HIROKI;NAKAMURA TSUYOSHI
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50;G06F9/45 主分类号 G06F17/50
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