| 摘要 |
A first contact hole (6) is formed penetrating a gate insulating film (5), on which a gate electrode (7g) is formed and simultaneously a first contact (7s, 7d) is formed in the first contact hole. A second contact hole (9) penetrating an interlayer insulating film (8) is formed, and a second contact (10) is formed in the second contact hole (9). A third contact hole (11) is formed penetrating a planarization film (26), and an electrode (40) is formed in the third contact hole (11). By using a plurality of contact holes for electrically connecting the electrode (40) and a semiconductor film (3), the aspect ratio of each contact hole can be reduced, thereby achieving improvement in yield, high-level integration due to a reduction in difference in area between upper and bottom surfaces of the contact, and other advantageous improvements. <IMAGE> |
