| 摘要 |
The phase-lock-loop circuit has a controllable oscillator and a source of a synchronising signal. A flip-flop responds to the sync. signal to generate a flip-flop output signal at a first state when an edge of the sync. signal occurs. The output signal alternates between the two states. A decoder applies the sync. signal to a decoder output via the flip-flop to generate a phase difference indicative signal. The phase difference indicative signal is generated in accordance with a phase difference between the sync. signal and an output signal of the oscillator, such that for phase differences that are both positive and negative, no other flip-flop is included in any signal path of the sync. signal between the source and decoder output. A low-pass filter receives the phase difference signal and is coupled to an oscillator control input for controlling it in a phase-lock-loop manner such that in steady state phase-lock operation, an edge of the oscillator output signal is aligned with the edge of the synchronizing signal.
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