发明名称 |
Semiconductor device, manufacturing method thereof, and displaly device |
摘要 |
A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a TFT which is in an on state is reduced to increase an on current. In addition, a carrier life time due to photoexcitation produced in the high concentration impurity region can be shortened to reduce light sensitivity. |
申请公布号 |
US2003059986(A1) |
申请公布日期 |
2003.03.27 |
申请号 |
US20020157046 |
申请日期 |
2002.05.30 |
申请人 |
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. |
发明人 |
SHIBATA HIROSHI |
分类号 |
G02F1/1362;H01L21/336;H01L21/77;H01L21/84;H01L27/12;H01L27/13;H01L29/786;(IPC1-7):H01L21/00 |
主分类号 |
G02F1/1362 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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