| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a system clock synchronization circuit capable of outputting right output data and a right enable signal synchronized with a system clock, instead of erroneous output data and an erroneous enable signal, even if a noise is superposed on an input clock signal. SOLUTION: Due to a noise superposed on a signal from an input clock CLK, flip-flop circuits 141 and 143 latch undefined data, which are output as an input enable signal Sen and input data Sdata through synchronization and timing delay circuits 12 and 13, respectively. However, mask signals S8 are generated based on signals S7 which are generated by synchronizing clock signals from the input clock CLK with a system clock SCLK and delaying the synchronized signals for a certain period. The undefined data are masked owing to the mask signals S8 and output signals S11 output from an AND gate 15 to which the mask signals S8 are input.</p> |
